PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 23

PXAH40KFBE

Manufacturer Part Number
PXAH40KFBE
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PXAH40KFBE

Cpu Family
XA
Device Core
80C51
Device Core Size
16b
Frequency (max)
30MHz
Interface Type
USART
Program Memory Type
ROMLess
Program Memory Size
Not Required
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.97V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Compliant

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Philips Semiconductors
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached USARTs. These modes are
Table 6. Rx DMA modes summary
1999 Sep 24
SDLC/HDLC
Rx Chaining
Periodic
Interrupt
Asynchronous
Character
Time Out
Asynchronous
Character
Match
Single-chip 16-bit microcontroller
Mode
DMA stores byte count in header in
memory with data packet.
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
Byte Count can be calculated by
software from the DMA address
pointer.
Byte Count can be calculated by
software from the DMA address
pointer.
Byte Count Source
Data FIFO 3
Data FIFO 1
Data FIFO 3
Data FIFO 1
Figure 5. Rx and Tx DMA Registers
At end of received packet
When Byte Counter reaches
zero and is reloaded by
DMA hardware from the byte
count register.
If no character is received
within a specified time out
period, then interrupt.
When matched character is
stored in memory.
Address Pointer
Address Pointer
Buffer Bound
Buffer Bound
Byte Count
Byte Count
Maskable Interrupt
DMA Control
FIFO Control
DMA Control
FIFO Control
Data FIFO 2
Data FIFO 0
Rx Time Out
Data FIFO 2
Data FIFO 0
Buffer Base
Buffer Base
Segment
Segment
23
summarized in Table 6. For full details on implementation and use,
see the XA-H4 User Manual .
When a complete or aborted SDLC/HDLC packet has
been received, the packet byte count and status
information are stored in memory with the packet. A
maskable interrupt is generated.
The DMA channel runs until commanded to stop by the
processor. It generates a maskable interrupt once per n
bytes, where n is the number written once into the byte
count register by the processor, thus an interrupt is
generated once every n received bytes.
Processor specifies time out period between incoming
characters. If no character is received within that time,
a maskable interrupt is generated.
There are four match registers, each incoming character
is received within that time, a maskable interrupt is
generated. When a matched character is stored in
memory by DMA, a maskable interrupt is generated.
Rx Channel
Tx Channel
SU01240
Description
Preliminary specification
XA-H4

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