PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 18

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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1.0 Signal/Pin Connection and Description
1.5 DETAILED SIGNAL/PIN DESCRIPTIONS
This section describes all the signals used in the PC8739x family. Some members of the PC8739x family implement
a subset of these signals. Refer to the table on page 3 to identify the functions relevant to a specific device.
1.5.1
1.5.2
1.5.3
IRRX1
IRRX2_IRSL0 68
IRSL1
IRSL2
IRSL3
IRTX
LAD3-0
LCLK
LDRQ
LFRAME
LRESET
SERIRQ
SMI
LPCPD
CLKRUN
CLKIN
Signal
Signal
Signal
Bus Interface
Clock
Infrared (IR)
69
67
71, 34
66
70
18-15
8
11
12
9
10
19
7
6
20
Pin/s
Pin(s)
Pin(s)
I/O Buffer Type Power Well
I/O
I/O
I/O
I/O Buffer Type Power Well
O
I/OD IN
I
I
OD
I/O Buffer Type Power Well
I/O
I/O
I
O
I
I
I
I
IN
IN
IN
IN
IN
O
TS
IN
T
T
PCI
IN
PCI
PCI
IN
IN
IN
IN
OD
IN
6/12
/O
/O
O
/O
TS
T
PCI
T
PCI
PCI
PCI
PCI
/OD
/O
/O
3/6
3/6
3/6
12
PCI
PCI
12
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
IR Receive 1. Primary input to receive serial data from the IR
transceiver. Monitored during power-off for wake-up event
detection.
IRRX2 - IR Receive 2. Auxiliary IR receiver input to support a
second transceiver. Monitored during power-off for wake-up event
detection.
IRSL3-0 IR Select. Outputs are used to control the IR transceivers.
Input for PnP identification of plug-in IR transceiver (dongle).
After reset, the dual function IRSLX pins wake up in input mode.
After the ID is read by the IR driver, these pins can be put into
output mode. The output mode is controlled by Serial Port 2.
IR Transmit. IR serial output data.
Clock In. Active clock input signal of 32.768 KHz, 14.318 MHz or
48 MHz.
LPC Address-Data. Multiplexed command, address bi-
directional data and cycle status.
LPC Clock. Same 33 MHz clock as the PCI clock.
LPC DMA Request. Encoded DMA request for LPC interface.
LPC Frame. Low pulse indicates the beginning of new LPC
cycle or termination of a broken cycle.
LPC Reset. Practically the PCI system reset.
Serial IRQ. The interrupt requests are serialized over a single
pin, where each IRQ level is delivered during a designated time
slot.
System Management Interrupt
Power Down. Indicates that power is going to be shut on the
LPC interface.
Clock Run. Indicates that LCLK is going to be stopped, and
requests full-speed LCK (same as PCI CLKRUN).
18
(Continued)
Description
Description
Description