PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 56

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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2.0 Device Architecture and Configuration
2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION
This section applies to the PC87392, PC87393 and PC87393F only.
2.15.1 General Description
The GPIO functional block includes 32 pins, arranged in four 8-bit ports (ports 0, 1, 2 and 3). All pins in ports 0 and 1 are
I/O, and have full event detection capability, enabling them to trigger the assertion of IRQ and SMI signals. Pins in ports 2
and 3 are I/O, but none of them has event detection capability. The twelve runtime registers associated with the four ports
are arranged in the GPIO address space as shown in Table 23. The GPIO base address is 16-byte aligned. Address bits 3-
0 are used to indicate the register offset.
2.15.2 Implementation
The standard GPIO port with event detection capability (such as ports 0 and 1) has four runtime registers. Each pin is asso-
ciated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard ports
that do not support event detection, and therefore differ from the generic model as follows:
They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers
GPEVEN2/3 and GPEVST2/3 are not available.
Only bits 3-0 are implemented in the GPIO Pin Configuration registers of ports 2 and 3. Bits 6-4, associated with the
event detection functionality, are reserved.
Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
Table 23. Runtime Registers in GPIO Address Space
Mnemonic
GPEVEN0 GPIO Event Enable 0
GPEVST0 GPIO Event Status 0
GPEVEN1 GPIO Event Enable 1
GPEVST1 GPIO Event Status 1
GPDO0
GPDO1
GPDO2
GPDO3
GPDI0
GPDI1
GPDI2
GPDI3
GPIO Data Out 0
GPIO Data In 0
GPIO Data Out 1
GPIO Data In 1
Data Out 2
Data In 2
Data Out 3
Data In 3
Register Name
56
(Continued)
Port
0
1
2
3
R/W1C
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO