PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 67

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

2.0 Device Architecture and Configuration
Type:
Bit
Name
Reset
5-4
3-2
1-0
Bit
7
6
User-Defined I/O Zone Enable. This bit enables the mapping of the User-Defined I/O zone to the X-Bus space.
The zone base address and size are defined by the X-Bus I/O Base Address High Byte register, X-Bus I/O Base
Address Low Byte register and the X-Bus I/O Size Configuration register.
0: Disabled (default)
1: Enabled
TST (Debug Port) Address Enable. When set, enables the mapping of I/O address 80h to the X-Bus space.
0: Disabled (default)
1: Enabled
RTC Address Enable. This bit controls the mapping of the RTC I/O address to the X-Bus space.
Bits
5 4
0 0
0 1
1 0
1 1
PM Address Enable. This bit controls the mapping of the PM I/O address to the X-Bus space.
Bits
3 2
0 0
0 1
1 0
1 1
KBC Address Enable. This bit controls the mapping of the KBC I/O address to the X-Bus space.
Bits
1 0
0 0
0 1
1 0
1 1
R/W
Defined I/O
Enable
User-
Zone
Mapping (hex)
Disabled (default)
70, 71
370, 371
70, 71, 72, 73
Mapping (hex)
Disabled (default)
62, 66
362, 366
Reserved
Mapping (hex)
Disabled (default)
60, 64
360, 364
Reserved
7
0
Address
Enable
TST
6
0
RTC Address Enable
5
0
Description
67
4
0
(Continued)
PM Address Enable
3
0
2
0
KBC Address Enable
1
0
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0