PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 50

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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2.0 Device Architecture and Configuration
2.12 PARALLEL PORT CONFIGURATION
2.12.1 General Description
The PC8739x Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard
or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP
mode).
The Parallel Port includes two groups of runtime registers, as follows:
The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-
isters are used and which address bits are used for the base address. See Tables 18 and 19 for a listing of all registers, their
offset addresses, and the associated modes.
•
•
A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h)
are used only in the Extended ECP mode.
A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.
Offset
400h
401h
402h
403h
404h
405h
1.
00h
01h
02h
03h
04h
05h
06h
07h
These registers are extended to the standard IEEE1284 registers. They
are accessible only when enabled by bit 4 of the Parallel Port Configura-
tion register (see Section 2.12.3).
Table 18. Parallel Port Registers at First Level Offset
Mnemonic
CNFGA
CNFGB
DATAR
CFIFO
DFIFO
AFIFO
ADDR
DATA0
DATA1
DATA2
DATA3
TFIFO
EDR
EAR
DCR
DTR
DSR
CTR
ECR
EIR
STR
1
1
1
0,1
3
4
0,1,2,3
4
0,1,2,3
4
4
4
4
4
4
2
3
6
7
7
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
Mode(s)
50
(Continued)
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
W
W
Data
ECP FIFO (Address)
Data (for EPP)
Status
Status (for EPP)
Control
Control (for EPP)
EPP Address
EPP Data Port 0
EPP Data Port 1
EPP Data Port 2
EPP Data Port 3
PP Data FIFO
ECP Data FIFO
Test FIFO
Configuration A
Configuration B
Extended Control
Extended Index
Extended Data
Extended Auxiliary Status
Register Name