NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 256

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NUC130VE3CN

Manufacturer Part Number
NUC130VE3CN
Description
IC MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC130VE3CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NUC130VE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC130VE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
PWM Output Enable Register (POE)
Register
POE
Bits
[3]
[2]
[1]
[0]
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
PWMA_BA+0x7C R/W
PWMB_BA+0x7C R/W
Descriptions
PWM3
PWM2
PWM1
PWM0
30
22
14
6
Reserved
R/W
29
21
13
5
Channel 3 Output Enable Register
1 = Enable PWM channel 3 output to pin
0 = Disable PWM channel 3 output to pin
Note: The corresponding GPIO pin also must be switched to PWM function
Channel 2 Output Enable Register
1 = Enable PWM channel 2 output to pin
0 = Disable PWM channel 2 output to pin
Note: The corresponding GPIO pin also must be switched to PWM function
Channel 1 Output Enable Register
1 = Enable PWM channel 1 output to pin
0 = Disable PWM channel 1 output to pin
Note: The corresponding GPIO pin also must be switched to PWM function
Channel 0 Output Enable Register
1 = Enable PWM channel 0 output to pin
0 = Disable PWM channel 0 output to pin
Note: The corresponding GPIO pin also must be switched to PWM function
Description
PWM Group A Output Enable Register for channel 0~3
PWM Group B Output Enable Register for channel 0~3
28
20
12
4
- 256 -
Reserved
Reserved
Reserved
PWM3
27
19
11
3
Publication Release Date: June 14, 2011
PWM2
26
18
10
2
PWM1
25
17
9
1
Revision V2.01
Reset Value
0x0000_0000
0x0000_0000
PWM0
24
16
8
0

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