NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 286

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1) Software writes the first data to SPI_TX0 register. The first data will be loaded to TX0 buffer if the
2) As long as the TX_FULL flag is 0, software can write the next data to SPI register in advance. In
3) As the first data transfer is finished and the TX_EMPTY flag is not 1, the data stored in SPI_TX0
4) Software writes the 3
5) The second data transfer sequence is finished. The data stored in SPI_TX0 will be loaded to TX0
TX_EMPTY flag is 1. And the TX_EMPTY flag will be cleared to 0 by hardware. The first data
transfer sequence starts.
this example, software writes the second data to SPI_TX0 register when the first data transfer
sequence is in progress. The TX_FULL flag will be set to 1 by hardware.
will be loaded to TX0 buffer and the TX_FULL flag will be cleared to 0 by hardware. The second
data transfer sequence will start automatically after a user-specified suspending interval.
buffer and the TX_FULL flag will be cleared to 0 by hardware. The 3
In master mode reception operation, the serial data is received from MISOx pin and stored at Rx0
buffer. When a data transfer is done and the RX_EMPTY flag is 1, the received data stored at
Rx0 buffer will be loaded into SPI_RX0 buffer and the RX_EMPTY flag will be cleared to 0.
Otherwise, when a data transfer is done and the RX_EMPTY flag is 0, the TX_FULL flag will be
set to 1, and the data stored at SPI_RX0 buffer will not be replaced by Rx0 buffer until software
read the SPI_RX0 buffer. Users can read the received data from SPI_RX0 buffer whenever the
RX_EMPTY flag is 0.
In slave mode, when the FIFO bit is set as 1, the GO_BUSY bit will be set as 1 by hardware
automatically. If users want to stop the slave mode SPI data transfer, both the FIFO bit and
GO_BUSY bit must be cleared to 0 by software.
In slave mode transmission operation, when software writes data to SPI_TX0 buffer, the data will
be loaded into Tx0 buffer if TX_EMPTY flag is 1. After a write operation, the TX_EMPTY flag will
be cleared to 0. The transmission will start when the slave device receives clock signal from
master. Users can write data to SPI_TX0 buffer whenever TX_FULL flag is 0. As a transfer is
done and the IE bit of SPI_CNTRL register is set to 1, SPI interrupt will be generated. The data
stored at SPI_TX0 buffer will be loaded to Tx0 buffer automatically if software has updated the
SPI_TX0 buffer. After all data have been transferred and software doesn’t update the SPI_TX0
buffer, the TX_EMPTY flag will be set to 1.
In slave mode reception operation, the serial data is received from MOSIx pin and stored at Rx0
buffer. The reception mechanism is similar to master mode.
The following is an example of FIFO mode operations. The SPI controller is configured as a
master with 8-bit data length in each transfer.
NuMicro™ NUC130/NUC140 Technical Reference Manual
rd
data to SPI_TX0 register. The TX_FULL flag will be set to 1 again.
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Publication Release Date: June 14, 2011
rd
data transfer sequence will
Revision V2.01