NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 305

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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NuMicro™ NUC130/NUC140 Technical Reference Manual
NOSLVSEL
Reserved
DIV_ONE
No Slave Select in Slave Mode
This is used to ignore the slave select signal in slave mode. The SPI controller
can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI
when it is set as a slave device.
0 = The controller is 4-wire bi-direction interface.
1 = The controller is 3-wire bi-direction interface in slave mode. When this bit
0 = The SPI clock rate is determined by the setting of SPI_DIVIDER register.
1 = Enable the DIV_ONE feature. The SPI clock rate equals the system clock
Note:
1. When this bit is set to 1, both the REORDER field and the VARCLK_EN
2. When this bit is set to 1, the TX_BIT_LEN can't be set as 1.
Note: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4], shall be
set as 1.
Reserved
SPI clock divider control
field must be configured as 0. In other words, the byte-reorder function,
byte suspend function and variable clock function must be disable.
is set as 1, the controller start to transmit/receive data after the GO_BUSY
bit active and the serial clock input.
rate.
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Publication Release Date: June 14, 2011
Revision V2.01