NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 386

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Synchronizations occur on edges from recessive to dominant, their purpose is to control the
distance between edges and Sample Points.
Edges are detected by sampling the actual bus level in each time quantum and comparing it with
the bus level at the previous Sample Point. A synchronization may be done only if a recessive bit
was sampled at the previous Sample Point and if the bus level at the actual time quantum is
dominant.
An edge is synchronous if it occurs inside of Sync_Seg, otherwise the distance between edge and
the end of Sync_Seg is the edge phase error, measured in time quanta. If the edge occurs before
Sync_Seg, the phase error is negative, else it is positive.
Two types of synchronization exist, Hard Synchronization and Re-synchronization.
A Hard Synchronization is done once at the start of a frame and inside a frame only when Re-
synchronizations occur.
After a hard synchronization, the bit time is restarted with the end of Sync_Seg,
regardless of the edge phase error. Thus hard synchronization forces the edge, which has caused
the hard synchronization to lie within the synchronization segment of the restarted bit time.
Re-synchronization leads to a shortening or lengthening of the bit time such that the position of
the sample point is shifted with regard to the edge.
When the phase error of the edge which causes Re-synchronization is positive, Phase_Seg1 is
lengthened. If the magnitude of the phase error is less than SJW, Phase_Seg1 is lengthened by
the magnitude of the phase error, else it is lengthened by SJW.
When the phase error of the edge, which causes Re-synchronization is negative, Phase_Seg2 is
shortened. If the magnitude of the phase error is less than SJW, Phase_Seg2 is shortened by
the magnitude of the phase error, else it is shortened by SJW.
When the magnitude of the phase error of the edge is less than or equal to the programmed
value of SJW, the results of Hard Synchronization and Re-synchronization are the same. If the
magnitude of the phase error is larger than SJW, the Re-synchronization cannot compensate the
phase error completely, an error (phase error - SJW) remains.
Only one synchronization may be done between two Sample Points. The Synchronizations
maintain a minimum distance between edges and Sample Points, giving the bus level time to
stabilize and filtering out spikes that are shorter than (Prop_Seg + Phase_Seg1)
Apart from noise spikes, most synchronizations are caused by arbitration. All nodes synchronize
“hard” on the edge transmitted by the “leading” transceiver that started transmitting first, but due
to propagation delay times, they cannot become ideally synchronized. The “leading” transmitter
does not necessarily win the arbitration, therefore the receivers have to synchronize themselves
to different transmitters that subsequently “take the lead” and that are differently synchronized to
the previously “leading” transmitter. The same happens at the acknowledge field, where the
transmitter and some of the receivers will have to synchronize to that receiver that “takes the
lead” in the transmission of the dominant acknowledge bit.
Synchronizations after the end of the arbitration will be caused by oscillator tolerance, when the
differences in the oscillator’s clock periods of transmitter and receivers sum up during the time
between synchronizations (at most ten bits). These summarized differences may not be longer
Hard Synchronization
Bit Re-synchronization
NuMicro™ NUC130/NUC140 Technical Reference Manual
- 386 -
Publication Release Date: June 14, 2011
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Revision V2.01