NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 470

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.16.4.4 Single-Cycle Scan Mode
In single-cycle scan mode, A/D conversion will sample and convert the specified channels once in
the sequence from the lowest number enabled channel to the highest number enabled channel.
An example timing diagram for single-cycle scan on enabled channels (0, 2, 3 and 7) is shown as
below:
1.
2.
3.
4.
NuMicro™ NUC130/NUC140 Technical Reference Manual
When the ADST bit of ADCR is set to 1 by software or external trigger input, A/D
conversion starts on the channel with the lowest number.
When A/D conversion for each enabled channel is completed, the result is sequentially
transferred to the A/D data register corresponding to each channel.
When the conversions of all the enabled channels are completed, the ADF bit in ADSR
is set to 1. If the ADC interrupt function is enabled, the ADC interrupt occurs.
After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D
converter enters idle state. If ADST is cleared to 0 before all enabled ADC channels
conversion done, ADC controller will finish current conversion and the result of the
lowest enabled ADC channel will become unpredictable. Note that, after clearing the
ADST bit to 0, the ADST bit must be kept at 0 at least one ADC clock period before
setting it to 1 again. If not, the A/D converter may not work.
Figure 5-103 Single-Cycle Scan on Enabled Channels Timing Diagram
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Publication Release Date: June 14, 2011
Revision V2.01