NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 285

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NuMicro™ NUC130/NUC140 Technical Reference Manual
FIFO Mode
The SPI controller supports FIFO mode when the FIFO in SPI_CNTRL[21] is set as 1. If the FIFO
mode is disabled, the user can only update the SPI_TX0 buffer after the current transfer is done.
In FIFO mode, the next one transmitted data can be written into the SPI_TX0 buffer in advance.
When the SPI controller operates with FIFO mode, the GO_BUSY bit of SPI_CNTRL register will
be controlled by hardware. It may result in wrong transfer If users modify the GO_BUSY bit.
Figure 5-59 FIFO mode Block Diagram
st
In master mode transmission operation, before the FIFO bit is set, users can write 1
data into
SPI_TX0 buffer. The TX_EMPTY flag will be cleared to 0. When the FIFO bit is set to 1, the data
stored at SPI_TX0 buffer will be loaded into the Tx0 buffer and the transmission starts
nd
immediately. Users can write the 2
data into SPI_TX0 buffer again and it will be loaded into the
st
transmitted bus buffer after the 1
transfer done. The SPI controller will insert a suspend interval
between two successive transactions in FIFO mode and the period of suspend interval is decided
by the setting of SP_CYCLE (SPI_CNTRL [15:12]). Users can write the transmitted data into
SPI_TX0 buffer whenever the TX_FULL flag is 0.
The transfer will be triggered automatically when the next transmitted data is updated in time. If
the SPI_TX0 buffer isn’t updated after all data transfer is done, the transfer will stop.
Publication Release Date: June 14, 2011
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Revision V2.01