IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 43

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

3.5.5
DETECTION
Random Signal Source (QRSS), Arbitrary Pattern (ARB) and Inband
Loopback (IB).
3.5.5.1 Pattern Generation
path, as selected by the PG_POS bit (b3, PG,...).
(b5~4, PG,...).
zero restriction according to ITU-T O.151 and AT&T TR62411 are
provided. They are: (2^20 - 1) QRSS per O.150-4.5, (2^15 - 1) PRBS
per O.152 and (2^11 - 1) PRBS per O.150, as selected by the
PRBG_SEL[1:0] bits (b1~0, PG,...).
(b7~0, ARBH~ARBM~ARBL,...).
The length of the IB code can be 3 to 8 bits, as determined by the
IBGL[1:0] bits (b5~4, IBL,...). The content is programmed in the IBG[7:0]
bits (b7~0, IBG,...).
bits (b5~4, PG,...) is set to ‘00’.
XCLK or the recovered clock from the received signal, as selected by
the PG_CK bit (b6, PG,...). The selected reference clock is also output
on RCLKn (if available).
XCLK
The transmit clock refers to the clock input on TCLKn (in Transmit Single
Rail NRZ Format mode and in Transmit Dual Rail NRZ Format mode) or
the clock recovered from the data input on TDPn and TDNn (in Transmit
Dual Rail RZ Format mode).
Functional Description
IDT82P2816
The pattern includes: Pseudo Random Bit Sequence (PRBS), Quasi-
The pattern can be generated in the receive path or the transmit
The pattern to be generated is selected by the PG_EN[1:0] bits
If PRBS is selected, three kinds of PRBS patterns with maximum
If ARB is selected, the content is programmed in the ARB[23:0] bits
If IB is selected, the IB generation is in compliance with ANSI T1.403.
The selected pattern is transmitted repeatedly until the PG_EN[1:0]
When pattern is generated in the receive path, the reference clock is
When pattern is generated in the transmit path, the reference clock is
In summary, do the followings step by step to generate pattern:
• Select the generation direction by the PG_POS bit (b3, PG,...);
• Select the reference clock by the PG_CK bit (b6, PG,...);
• Select the PRBS pattern by the PRBG_SEL[1:0] bits (b1~0, PG,...)
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
when PRBS is to be generated; program the ARB pattern in the
ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) when ARB is to be
generated; or set the length and the content of the IB code in the
IBGL[1:0] bits (b5~4, IBL,...) and in the IBG[7:0] bits (b7~0, IBG,...)
respectively when IB is to be generated;
1
in E1 mode.
or the transmit clock, as selected by the PG_CK bit (b6, PG,...).
PRBS, QRSS, ARB AND IB PATTERN GENERATION AND
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
43
can be optionally implemented after the pattern is generated:
should be encoded by using AMI or B8ZS (for T1/J1) / HDB3 (for E1) in
Receive Dual Rail NRZ Format mode, Receive Dual Rail RZ Format
mode and Receive Dual Rail Sliced mode. The encoding rule is selected
by the R_CODE bit (b2, RCF1,...).
should be encoded by using AMI or B8ZS (for T1/J1) / HDB3 (for E1).
The encoding rule is selected by the T_CODE bit (b2, TCF1,...).
tion. If they are generated in the same direction, the generated pattern
will overwrite the generated AIS.
RTIPn/RRINGn
• Set the PG_EN[1:0] bits (b5~4, PG,...) to generate the pattern.
If PRBS or ARB is selected to be generated, the following two steps
• Insert a single bit error by writing ‘1’ to the ERR_INS bit (b5,
• Invert the generated pattern by setting the PAG_INV bit (b2,
If pattern is generated in the receive path, the generated pattern
If pattern is generated in the transmit path, the generated pattern
The pattern generation is shown in Figure-22 and Figure-23.
TTIPn/TRINGn
The priority of pattern generation is higher than that of AIS genera-
ERR
PG
PRBS generation
PRBG_SEL[1:0]
24 bits ARB
,...).
ARB[23:0]
,...) ;
2^11-1
2^15-1
2^20-1
Figure-22 Pattern Generation (1)
Figure-23 Pattern Generation (2)
PG_POS
PG_EN[1:0]
CHn
pattern generator
PRBS/ARB/IB
PG_EN[1:0]
Single bit error
ERR_INS
insert
PG_CK
February 6, 2009
TDPn/TDNn/TCLKn
RDPn/RDNn/RCLKn
PAG_INV
invert
XCLK
TCLK/RCLK