IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 62

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

Table-25 Interrupt Summary
3.7
25. Among them, No.1 to No.19 are per-channel interrupt sources, while
No. 20 is a global interrupt source.
will cause the corresponding Status bit to be set to ‘1’. And selected by
the Interrupt Trigger Edges Select bit, either a transition from ‘0’ to ‘1’ or
any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ of the Status bit will cause
the Interrupt Status bit to be set to ‘1’, which indicates the occurrence of
an interrupt event.
event will cause the corresponding Interrupt Status Bit to be set to ‘1’.
Functional Description
IDT82P2816
No.
10
12
13
14
15
16
17
18
19
20
11
1
2
3
4
5
6
7
8
9
There are altogether 20 kinds of interrupt sources as listed in Table-
For interrupt sources from No.1 to No.10, the occurrence of the event
For interrupt sources from No.11 to No.20, the occurrence of the
TCLKn is missing.
LLOS is detected.
SLOS is detected.
TLOS is detected.
LAIS is detected.
SAIS is detected.
TOC is detected.
The PRBS/ARB pattern is detected syn-
chronized.
Activate IB code is detected.
Deactivate IB code is detected.
The FIFO of the RJA is overflow or
underflow.
The FIFO of the TJA is overflow or
underflow.
Waveform amplitude is overflow.
SBPV is detected.
LBPV is detected.
SEXZ is detected.
LEXZ is detected.
The ERRCH and ERRCL registers are
overflowed.
One second time is over.
PRBS/ARB error is detected.
INTERRUPT SUMMARY
Interrupt Source
SLOS_S (b1, STAT0,...)
TLOS_S (b2, STAT0,...)
LLOS_S (b0, STAT0,...)
LAIS_S (b6, STAT1,...)
SAIS_S (b7, STAT1,...)
TOC_S (b4, STAT0,...)
IBD_S (b0, STAT1,...)
IBA_S (b1, STAT1,...)
PA_S (b5, STAT1,...)
TCKLOS_S (b3,
Status Bit
STAT0,...)
-
-
-
-
-
-
-
-
-
-
TLOS_IES (b2, INTES,...)
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Interrupt Trigger Edges
LOS_IES (b1, INTES,...)
LOS_IES (b1, INTES,...)
TOC_IES (b4, INTES,...)
AIS_IES (b6, INTES,...)
AIS_IES (b6, INTES,...)
PA_IES (b5, INTES,...)
IB_IES (b0, INTES,...)
IB_IES (b0, INTES,...)
62
TCKLOS_IES (b3,
or by the corresponding interrupt mask bit individually. For all the inter-
rupt sources, if not masked, the occurrence of the interrupt event will
trigger an interrupt indicated by the INT pin. For per-channel interrupt
sources, if not masked, the occurrence of the interrupt event will also
cause the corresponding INT_CHn bit (INTCH1~3) to be set ‘1’.
rupt Status bit. The INT_CHn bit (INTCH1~3) will not be cleared until all
the interrupts in the corresponding channel are acknowledged. The INT
pin will be inactive until all the interrupts are acknowledged. Refer to
Figure-40 for interrupt service flow.
Select Bit
INTES,...)
All the interrupt can be masked by the GLB_IM bit (b1, GCF) globally
An interrupt event is cleared by writing ‘1’ to the corresponding Inter-
-
-
-
-
-
-
-
-
-
-
CNTOV_IS (b0, INTS2,...) CNTOV_IM (b0, INTM2,...)
SLOS _IS (b1, INTS0,...)
LLOS_IS (b0, INTS0,...)
TLOS_IS (b2, INTS0,...)
SBPV_IS (b5, INTS2,...)
SEXZ_IS (b3, INTS2,...)
LBPV_IS (b4, INTS2,...)
LEXZ_IS (b2, INTS2,...)
SAIS_IS (b7, INTS1,...)
LAIS_IS (b6, INTS1,...)
ERR_IS (b1, INTS2,...)
TOC_IS (b4, INTS0,...)
DAC_IS (b7, INTS0,...)
TMOV_IS (b0, INTTM)
RJA_IS (b5, INTS0,...)
IBD_IS (b0, INTS1,...)
TJA_IS (b6, INTS0,...)
IBA_IS (b1, INTS1,...)
PA_IS (b5, INTS1,...)
Interrupt Status Bit
TCKLOS_IS (b3,
INTS0,...)
SLOS_IM (b1, INTM0,...)
LLOS_IM (b0, INTM0,...)
TLOS_IM (b2, INTM0,...)
SBPV_IM (b5, INTM2,...)
LBPV_IM (b4, INTM2,...)
SEXZ_IM (b3, INTM2,...)
LEXZ_IM (b2, INTM2,...)
SAIS_IM (b7, INTM1,...)
LAIS_IM (b6, INTM1,...)
TOC_IM (b4, INTM0,...)
DAC_IM (b7, INTM0,...)
ERR_IM (b1, INTM2,...)
RJA_IM (b5, INTM0,...)
TJA_IM (b6, INTM0,...)
IBA_IM (b1, INTM1,...)
IBD_IM (b0, INTM1,...)
PA_IM (b5, INTM1,...)
TMOV_IM (b0, GCF)
Interrupt Mask Bit
TCKLOS_IM (b3,
February 6, 2009
INTM0,...)