IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 95

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

PG - Pattern Generation Control Register
Address: 010H, 050H, 090H, 0D0H, 110H, 150H, 190H, 1D0H, (CH1~CH8)
Type: Read / Write
Default Value: 00H
Programming Information
IDT82P2816
5 - 4
1 - 0
Bit
7
6
3
2
210H, 250H, 290H, 2D0H, 310H, 350H, 390H, 3D0H, (CH9~CH16)
7D0H (CH0)
7
-
PRBG_SEL[1:0] These bits are valid only when the PRBS pattern is generated. They select the PRBS pattern.
PG_EN[1:0]
PAG_INV
PG_POS
PG_CK
Name
-
PG_CK
6
Reserved.
This bit selects the reference clock when the pattern (including PRBS, ARB & IB) is generated.
When the pattern is generated in the receive path:
0: XCLK. (default)
1: Recovered clock from the received signal.
When the pattern is generated in the transmit path:
0: XCLK. (default)
1: Transmit clock, i.e., the clock input on TCLKn (in Transmit Single Rail NRZ Format mode and in Transmit Dual Rail NRZ For-
mat mode) or the clock recovered from the data input on TDPn and TDNn (in Transmit Dual Rail RZ Format mode)
These bits select the pattern to be generated.
00: Disable. (default)
01: PRBS.
10: ARB.
11: IB.
This bit selects the pattern (including PRBS, ARB & IB) generation direction.
0: Transmit path. (default)
1: Receive path.
This bit controls whether to invert the generated PRBS/ARB pattern.
0: Normal. (default)
1: Invert.
00: 2
01: 2
1X: 2
20
15
11
- 1 QRSS. (default)
- 1 PRBS.
- 1 PRBS.
PG_EN1
5
PG_EN0
4
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
95
PG_POS
3
Description
PAG_INV
2
PRBG_SEL1
1
February 6, 2009
PRBG_SEL0
0