PEB 20954 HT V1.1 Infineon Technologies, PEB 20954 HT V1.1 Datasheet - Page 88

• Manufacturer Part Number: PEB 20954 HT V1.1
• Description: IC SIDEC T/E 32CHAN TQFP-144-8
• Manufacturer: Infineon Technologies

Specifications of PEB 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 4
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection, Maskable Disabling, Voiceband Echo Cancelling
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEB20954HTV1.1T; PEB20954HTV11XP; SP000007504; SP000007506

*Note: In the case of no A-/ -Law conversion (same law at near and far end side) the
PCM encoding law can temporarily be changed by any conversion disabling source ( P,
UCC FX-Bit or serial control signal) if GCONVDISLAW is different from GALAWNE/
GALAWFE.
CHCTRL0-31[7:0] (Addr.: 40H-5FH): Individual channel control, write protected,
Reset value = 00H
The upper three bits ICONVDISLAW, IALAWNE and IALAWFE are only enabled if
CONFLAW.CHIND = '1'. For explanation of law conversion see also
ICONVDISLAW
IALAWNE
IALAWFE
CONVDIS
Data Sheet
DISLAW
ICONV
IALAW
NE
'0': -Law PCM encoding at far end side (RI and SO)
Determines the valid PCM-law of the corresponding channel if the
PCM-Law conversion for this channel is disabled (CONVDIS = '1')
and channel individual settings are enabled
(Bit CONFLAW.CHIND = '1')
'1': The corresponding PCM channel is A-Law en/decoded if
'0': The corresponding PCM channel is µ-Law en/decoded if
'1': The corresponding PCM channel is A-Law PCM en/decoded at
'0': The corresponding PCM channel is µ-Law PCM en/decoded at
'1': The corresponding PCM channel is A-Law PCM en/decoded at
'0': The corresponding PCM channel is µ-Law PCM en/decoded at
'1': Disables the PCM Law conversion (GALAWNE, GALAWFE,
if CHIND = '0' and CONVDIS = '0'
if CHIND = '0' and CONVDIS = '0'
conversion is disabled*
conversion is disabled*
the near end side (RO and SI) if CONFLAW.CHIND = '1'
and CONVDIS = '0'
the near end side (RO and SI) if CONFLAW.CHIND = '1'
and CONVDIS = '0'
the far end side (RI and SO) if CONFLAW.CHIND = '1'
and CONVDIS = '0'
the far end side (RI and SO) if CONFLAW.CHIND = '1'
and CONVDIS = '0'
IALAWNE, IALAWFE) for the corresponding channel. The valid
encoding Law for this channel is determined by the values of the
Bits ICONVDISLAW of this register if channel individual settings
are configured (CHIND = '1') or the settings of the global register
CONFLAW.GCONVDISLAW, if global configuration is configured
IALAW
FE
CONV
DIS
88
FREEZE NLPDIS
Register Description
ABLE
Figure
DIS
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
10.
CTRL
ENP