PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 201
PEF 20532 F V1.3
Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20532_F_V1.3.pdf
(282 pages)
Specifications of PEF 20532 F V1.3
Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
PEF20532FV13XP
SP000007511
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Data Sheet
Register 61
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 62
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
7
7
0
0
0
0
XAD1
Transmit Address 1 Register
XAD2
Transmit Address 2 Register
6
6
0
0
0
0
read/write
00
Channel A
3E
written by CPU; read and evaluated by SEROCCO-M
read/write
00
Channel A
3F
written by CPU; read and evaluated by SEROCCO-M
H
H
H
H
XAD1 (high byte)
5
5
0
0
0
0
Channel B
8E
Channel B
8F
Transmit Address (high)
or XAD2 (RESPONSE)
Transmit Address (low)
or XAD1 (COMMAND)
H
H
XAD2 (low byte)
5-201
4
4
0
0
0
0
3
3
0
0
0
0
Register Description (XAD1)
2
2
0
0
0
0
1
1
0
0
0
0
0
PEB 20532
PEF 20532
2000-09-14
XAD1_0
0
0
0
0
0
0
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