PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 49
PEF 20532 F V1.3
Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20532_F_V1.3.pdf
(282 pages)
Specifications of PEF 20532 F V1.3
Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
PEF20532FV13XP
SP000007511
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The clocking concept is illustrated in a block diagram manner in the following figure:
Additional control signals are not illustrated (please refer to the detailed clock mode
descriptions below).
Figure 13
Data Sheet
Clock Supply Overview
settings controlled by:
register CCR0, bit field 'CM'
selects the clock mode number
register CCR0, bit 'SSEL'
selects the additional a/b option
TTL
Oscillator
or
CRYSTAL
3a
7a
Transmitter
0b
3b
7b
DPLL
2b
6b
f
f
DPLL
TRM
1
5a
0b
6a/b
7a/b
49
0a
2a
6a
4
5b
BRG
f
BRG
2a/b
3a/b
16:1
f
BRG/16
2a/b
3a
6a/b
7a
Receiver
3b
7b
f
RxCLK
f
REC
0a/b
1
5a/b
4
Functional Overview
f
TxCLK
PEB 20532
PEF 20532
2000-09-14
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