SC16C850IBS,151 NXP Semiconductors, SC16C850IBS,151 Datasheet - Page 25
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SC16C850IBS,151
Manufacturer Part Number
SC16C850IBS,151
Description
IC UART SGL-CH 3.3V 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C850IBS151.pdf
(55 pages)
Specifications of SC16C850IBS,151
Package / Case
32-VFQFN Exposed Pad
Features
Programmable
Number Of Channels
1, UART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.5 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4778
935283103151
935283103151
NXP Semiconductors
SC16C850
Product data sheet
7.3.1 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO
trigger levels.
Table 10.
[1]
[2]
Table 11.
[1]
Bit
7:6
5:4
3
2
1
0
FCR[7]
0
0
1
1
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
FCR[7:6] Receive trigger level in 32-byte FIFO mode
FCR[5:4] Transmit trigger level in 32-byte FIFO mode
FCR[3]
FCR[2]
FCR[1]
FCR[0]
Symbol
FIFO Control Register bits description
RCVR trigger levels
FCR[6]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
These bits are used to set the trigger levels for receive FIFO interrupt and flow
control. The SC16C850 will issue a receive ready interrupt when the number of
characters in the receive FIFO reaches the selected trigger level. Refer to
Table
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850 will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table
reserved
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 2 — 11 November 2010
11.
12.
RX FIFO trigger level (bytes) in 32-byte FIFO mode
8
16
24
28
Section
Section
7.16,
7.15,
Section
Section
7.17,
7.17,
Section
Section
[1]
[2]
.
.
7.18.
7.18.
Section 6.4 “FIFO
SC16C850
© NXP B.V. 2010. All rights reserved.
operation”).
[1]
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