SC16C850IBS,151 NXP Semiconductors, SC16C850IBS,151 Datasheet - Page 27

• Manufacturer Part Number: SC16C850IBS,151
• Description: IC UART SGL-CH 3.3V 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850IBS,151

• Package / Case: 32-VFQFN Exposed Pad
• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 2.5 V ~ 3.3 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4778; 935283103151

NXP Semiconductors
SC16C850
Product data sheet
7.5 Line Control Register (LCR)
Table 14.
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15.
Table 16.
Table 17.
Bit
0
Bit
7
6
5:3
2
1:0
LCR[5]
X
0
0
1
1
LCR[2]
0
1
1
Symbol
ISR[0]
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Interrupt Status Register bits description
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[4]
X
0
1
0
1
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
All information provided in this document is subject to legal disclaimers.
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Stop bits. The length of stop bit is specified by this bit in conjunction with the
Word length bits 1, 0. These two bits specify the word length to be
Description
INT status.
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
Programs the parity conditions (see
programmed word length (see
transmitted or received (see
Rev. 2 — 11 November 2010
LCR[3]
0
1
1
1
1
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Stop bit length (bit times)
1
1
2
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
1
⁄
2
Table
Table
…continued
18).
Table
17).
16).
SC16C850
© NXP B.V. 2010. All rights reserved.
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