SC16C850IBS,151 NXP Semiconductors, SC16C850IBS,151 Datasheet - Page 34
![IC UART SGL-CH 3.3V 32-HVQFN](/photos/6/51/65170/568-32-hvqfn_sml.jpg)
SC16C850IBS,151
Manufacturer Part Number
SC16C850IBS,151
Description
IC UART SGL-CH 3.3V 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C850IBS151.pdf
(55 pages)
Specifications of SC16C850IBS,151
Package / Case
32-VFQFN Exposed Pad
Features
Programmable
Number Of Channels
1, UART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.5 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4778
935283103151
935283103151
NXP Semiconductors
SC16C850
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock Prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 27.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 28.
[1]
This register hold values for the clock prescaler.
Table 29.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
FLWCNTH[7:0]
FLWCNTL[7:0]
CLKPRES[7:4]
Symbol
Symbol
Symbol
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register bits description
All information provided in this document is subject to legal disclaimers.
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 2 — 11 November 2010
Section
Section
This register stores the programmable HIGH threshold level for
This register stores the programmable LOW threshold level for
reserved
Clock Prescaler value. Reset to 0.
Description
hardware and software flow control for 128-byte FIFO mode
Description
hardware and software flow control for 128-byte FIFO mode
Description
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section
Section
Section
6.5.
6.5.
7.3.
7.3.
7.3.
Table 27
Table 28
shows the FLWCNTH
shows the FLWCNTL
SC16C850
© NXP B.V. 2010. All rights reserved.
[1]
[1]
34 of 55
.
.