SC16C850IBS,151 NXP Semiconductors, SC16C850IBS,151 Datasheet - Page 26

• Manufacturer Part Number: SC16C850IBS,151
• Description: IC UART SGL-CH 3.3V 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850IBS,151

• Package / Case: 32-VFQFN Exposed Pad
• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 2.5 V ~ 3.3 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4778; 935283103151

NXP Semiconductors
SC16C850
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 12.
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The SC16C850 provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits.
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 13.
Table 14.
FCR[5]
0
0
1
1
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[5]
0
0
0
0
0
0
1
TX FIFO trigger levels
Interrupt source
Interrupt Status Register bits description
FCR[4]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
ISR[4]
0
0
0
0
0
1
0
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
Description
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C850 mode.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
interrupt priority levels 1, 2, and 3 (see
Rev. 2 — 11 November 2010
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
ISR[3]
0
0
1
0
0
0
0
TX FIFO trigger level (bytes) in 32-byte FIFO mode
16
8
24
30
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
Table 13 “Interrupt source”
ISR[0]
0
0
0
0
0
0
0
Table
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/
Special character
CTS, RTS change of state
Section 6.4 “FIFO
13).
SC16C850
© NXP B.V. 2010. All rights reserved.
operation”).
shows the
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