SC16IS762IBS,157 NXP Semiconductors, SC16IS762IBS,157 Datasheet - Page 21
![IC DUAL UART 64BYTE 32HVQFN](/photos/6/51/65170/568-32-hvqfn_sml.jpg)
SC16IS762IBS,157
Manufacturer Part Number
SC16IS762IBS,157
Description
IC DUAL UART 64BYTE 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16IS752IBS151.pdf
(59 pages)
Specifications of SC16IS762IBS,157
Features
Low Current
Number Of Channels
2, DUART
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935279293157
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
Table 10.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Enhanced Features Registers are only accessible when LCR = 0xBF.
Register
address
Special register set
0x00
0x01
Enhanced register set
0x02
0x04
0x05
0x06
0x07
These registers are accessible only when LCR[7] = logic 0.
This bit can only be modified if register bit EFR[4] is enabled.
These bits are reserved and should be set to logic 0.
After Receive FIFO or Transmit FIFO reset (through FCR [1:0]), the user must wait at least 2
Burst reads on the serial interface (that is, reading multiple elements on the I
without de-asserting the CS pin), should not be performed on the IIR register.
These registers are accessible only when EFR[4] = logic 1, and MCR[2] = logic 1.
These registers apply to both channels.
IrDA mode slow/fast for SC16IS762, slow only for SC16IS752.
The Special Register set is accessible only when LCR[7] = logic 1 and LCR is not 0xBF.
SC16IS752/SC16IS762 internal registers
Register
DLL
DLH
EFR
XON1
XON2
XOFF1
XOFF2
[9]
[10]
Bit 7
bit 7
bit 7
Auto CTS
bit 7
bit 7
bit 7
bit 7
Bit 6
bit 6
bit 6
Auto RTS
bit 6
bit 6
bit 6
bit 6
…continued
Bit 5
bit 5
bit 5
special
character
detect
bit 5
bit 5
bit 5
bit 5
2
C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
Bit 4
bit 4
bit 4
enable
enhanced
functions
bit 4
bit 4
bit 4
bit 4
T
clk
Bit 3
bit 3
bit 3
software flow
control bit 3
bit 3
bit 3
bit 3
bit 3
of XTAL1 before reading or writing data to RHR and THR respectively.
Bit 2
bit 2
bit 2
software flow
control bit 2
bit 2
bit 2
bit 2
bit 2
Bit 1
bit 1
bit 1
software flow
control bit 1
bit 1
bit 1
bit 1
bit 1
Bit 0
bit 0
bit 0
software flow
control bit 0
bit 0
bit 0
bit 0
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W