SC16IS762IBS,157 NXP Semiconductors, SC16IS762IBS,157 Datasheet - Page 26
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SC16IS762IBS,157
Manufacturer Part Number
SC16IS762IBS,157
Description
IC DUAL UART 64BYTE 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16IS752IBS151.pdf
(59 pages)
Specifications of SC16IS762IBS,157
Features
Low Current
Number Of Channels
2, DUART
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935279293157
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
8.7 Modem Control Register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem.
Table 19.
[1]
Bit
7
6
5
4
3
2
1
0
MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
Modem Control Register bits description
[1]
[1]
[1]
Table 19
Dual UART with I
Description
Clock divisor.
IrDA mode enable.
Xon Any.
Enable loopback.
reserved
TCR and TLR enable.
RTS
DTR. If GPIO5 or GPIO1 is selected as DTR modem pin through
IOControl register bit 1 or bit 2, the state of DTR pin can be controlled as
below. Writing to IOState bit 5 or bit 1 will not have any effect on the DTR
pin.
Rev. 07 — 19 May 2008
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
logic 0 = normal UART mode
logic 1 = IrDA mode
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
logic 0 = normal operating mode
logic 1 = enable local Loopback mode (internal). In this mode the
MCR[1:0] signals are looped back into MSR[4:5] and the TX output is
looped back to the RX input internally.
logic 0 = disable the TCR and TLR register
logic 1 = enable the TCR and TLR register
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW). In Loopback mode,
controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled
by hardware flow control.
logic 0 = force DTR output to inactive (HIGH)
logic 1 = force DTR output to active (LOW)
shows Modem Control Register bit settings.
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
© NXP B.V. 2008. All rights reserved.
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