SC16IS762IBS,157 NXP Semiconductors, SC16IS762IBS,157 Datasheet - Page 24
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SC16IS762IBS,157
Manufacturer Part Number
SC16IS762IBS,157
Description
IC DUAL UART 64BYTE 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16IS752IBS151.pdf
(59 pages)
Specifications of SC16IS762IBS,157
Features
Low Current
Number Of Channels
2, DUART
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935279293157
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
8.5 Interrupt Identification Register (IIR)
8.6 Line Control Register (LCR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.
Table 13.
Table 14.
[1]
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.
shows the Line Control Register bit settings.
Table 15.
Bit
7:6
5:1
0
Priority
level
1
2
2
3
4
5
6
7
Bit
7
6
Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState
register.
Symbol
IIR[7:6]
IIR[5:1]
IIR[0]
Symbol
LCR[7]
LCR[6]
Interrupt Identification Register bits description
Interrupt source
IIR[5]
0
0
0
0
0
1
0
1
Line Control Register bits description
Table 13
IIR[4]
0
0
0
0
0
1
1
0
Dual UART with I
Description
Mirror the contents of FCR[0].
5-bit encoded interrupt. See
Interrupt status.
Description
Divisor latch enable.
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Rev. 07 — 19 May 2008
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
IIR[3]
0
1
0
0
0
0
0
0
shows Interrupt Identification Register bit settings.
IIR[2]
1
1
1
0
0
0
0
0
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
IIR[1]
1
0
0
1
0
0
0
0
Table
IIR[0]
0
0
0
0
0
0
0
0
14.
Source of the interrupt
Receive Line Status error
Receiver time-out interrupt
RHR interrupt
THR interrupt
modem interrupt
input pin change of state
received Xoff signal/special
character
CTS, RTS change of state
from active (LOW) to
inactive (HIGH)
© NXP B.V. 2008. All rights reserved.
Table 15
[1]
24 of 59
[1]