SC16IS762IBS,157 NXP Semiconductors, SC16IS762IBS,157 Datasheet - Page 9
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SC16IS762IBS,157
Manufacturer Part Number
SC16IS762IBS,157
Description
IC DUAL UART 64BYTE 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16IS752IBS151.pdf
(59 pages)
Specifications of SC16IS762IBS,157
Features
Low Current
Number Of Channels
2, DUART
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935279293157
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
SC16IS762IBS
NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
Fig 5.
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in
RTS functional timing
receive
FIFO
RTS
read
RX
7.2.1 Auto-RTS
Figure 5
are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in
TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The
sending device (for example, another UART) may send an additional character after the
trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.
start
Fig 4.
character
shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS
N
Auto flow control (Auto-RTS and Auto-CTS) example
FIFO
FIFO
TX
RX
stop
UART 1
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
Dual UART with I
CONTROL
Rev. 07 — 19 May 2008
FLOW
FLOW
start
character
N + 1
1
RTS
CTS
RX
TX
2
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
stop
TX
CTS
RX
RTS
TO SERIAL
SERIAL TO
PARALLEL
N
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
N + 1
Section
© NXP B.V. 2008. All rights reserved.
002aab040
start
7.2.1.
FIFO
FIFO
RX
TX
002aab656
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