SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 6
SC28L201A1DGG,118
Manufacturer Part Number
SC28L201A1DGG,118
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,118
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277824118
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
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Philips Semiconductors
5. Pinning information
Table 2:
See
9397 750 13138
Product data sheet
Symbol
MODE_IM
D0 to D7
CEN
WRN
Fig 3. Pin configuration for TSSOP48; 80xxx mode
MODE_IM
RESET
Figure
IACKN
RXD
V
V
V
V
V
D7
D6
D5
D4
D3
D2
D1
D0
DD
A6
A5
A4
A3
DD
A2
A1
A0
DD
SS
SS
3.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin description for 80xxx bus interface (Intel)
1
2
3
4
5
6
7
8
9
Pin
19
18, 17, 16,
15, 12, 11,
10, 9
26
27
5.1 Pinning
5.2 Pin description
SC28L201A1DGG
80xxx mode
Type
I
I/O
I
I
Description
Bus configuration. When HIGH or not connected configures the bus interface to
the conditions shown in this table.
Data bus. Bidirectional 3-state data bus used to transfer commands, data and status
between the UART and the CPU. D0 is the least significant bit.
Chip Enable. Active LOW input signal. When LOW, data transfers between the CPU
and the UART are enabled on D[0:7] as controlled by the WRN, RDN and A6 to A0
inputs. When HIGH, places the D[0:7] lines in the 3-state condition.
Write strobe. When LOW and CEN is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
002aab421
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Rev. 01 — 31 October 2005
X2
X1/SCLK
IRQN
TXD
I/O0A
I/O1A
I/O2A
I/O3A
I/O4A
I/O5A
I/O6A
I/O7A
V
V
V
I/O0B
I/O2B
I/O3B
I/O4B
I/O6B
RDN
WRN
CEN
V
SS
SS
DD
SS
Fig 4. Pin configuration for TSSOP48; 68000 mode
MODE_IM
RESETN
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
IACKN
RXD
V
V
V
V
V
D7
D6
D5
D4
D3
D2
D1
D0
DD
A6
A5
A4
A3
DD
A2
A1
A0
DD
SS
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
SC28L201A1DGG
68xxx mode
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
002aab422
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IRQN
TXD
V
I/O0B
I/O2B
I/O3B
I/O4B
I/O6B
DACKN
R/WN
CEN
V
X2
X1/SCLK
I/O0A
I/O1A
I/O2A
I/O3A
I/O4A
I/O5A
I/O6A
I/O7A
V
V
SS
SS
DD
SS
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