SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 65
SC28L201A1DGG,118
Manufacturer Part Number
SC28L201A1DGG,118
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,118
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277824118
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
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Philips Semiconductors
9397 750 13138
Product data sheet
8.4.3 Counter/Timer clock source (CTCS0 and CTCS1)
Remark: Writing to this register removes the control established in the counter/timer
portion of the ACR in the default register map.
Table 40:
Bit
7:6
5:4
3:0
Symbol
CTCS0 and CTCS1 - Counter/Timer clock source registers (address 0x24, 0x2C)
bit description
Description
reserved
Mode control
Clock selection
Rev. 01 — 31 October 2005
00 = selects Counter mode. Generates a timing edge.
01 = selects Timer mode. Generates a square wave.
10 = reserved
11 = selects Timer Pulse mode. Generates periodic pulses twice the
frequency as in Timer mode. Pulse width is one cycle of the clock as it is
delivered to the C/T, that is, after any prescale.
0000 = external I/O2A (for CT 0); I/O7A (for CT 1)
0001 = external I/O2A/16 (for CT 0); I/O7A/16 (for CT 1)
0010 = SCLK
0011 = SCLK/2
0100 = SCLK/16
0101 = SCLK/32
0110 = SCLK/64
0111 = SCLK/128
1000 = TxCA1X
1001 = reserved
1010 = reserved
1011 = reserved
1100 = Rx Character Count (Ch A) Clock is RxFIFO A load pulse
1101 = reserved
1110 = reserved
1111 = reserved
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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