SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 86
SC28L201A1DGG,118
Manufacturer Part Number
SC28L201A1DGG,118
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,118
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277824118
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
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Philips Semiconductors
9. Register maps
Table 77:
[1]
9397 750 13138
Product data sheet
A[6:0]
001 0000 (0x10)
001 0001 (0x11)
001 0010 (0x12)
001 0011 (0x13)
001 0100 (0x14)
001 0101 (0x15)
001 0110 (0x16)
001 0111 (0x17)
001 1000 (0x18)
001 1001 (0x19)
001 1010 (0x1A)
001 1011 (0x1B) Input Port Change Register Upper (IPCRU B)
001 1100 (0x1C) Input Port Change Register Lower (IPCRL B)
001 1101 (0x1D) Input Port Register (IPR B)
001 1110 (0x1E) Counter Timer Value Register Upper (CTVU 1)
001 1111 (0x1F)
This register configures the whole chip.
Register map detail
Read
Receiver FIFO Fill Level (RxFL A)
Transmitter FIFO Empty level (TxEL A)
Enhanced Operation Status (EOS)
Input Port Change Register Upper (IPCRU A)
Input Port Change Register Lower (IPCRL A)
Input Port Register (IPR A)
Counter Timer Value Register Upper (CTVU 0)
Counter Timer Value Register Lower (CTVL 0)
Counter Timer Value Register Lower (CTVL 1)
The registers of the SC28L201 are loosely partitioned into two groups: those used in
controlling data channels, and those used in handling the actual data flow and status.
Below is shown the general configuration of all the registers addressed. The
“Register map summary”
Any programming using the SC28L201 as it is intended would always use the address
space from 0x10 through 0x7F.
Rev. 01 — 31 October 2005
shows the configuration of the address.
[1]
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Write
Set Output Port Register (SOPR A)
Reset Output Port Register (ROPR A)
Command Register Extension (CRx A)
I/O Port Configuration Register 0 (I/OPCR 0)
I/O Port Configuration Register 1 (I/OPCR 1)
Counter Timer Preset Register Upper (CTPU 0)
Counter Timer Preset Register Lower (CTPL 0)
Set Output Port Register (SOPR B)
Reset Output Port Register (ROPR B)
Command Register Extension (CRx B)
I/O Port Configuration Register 2 (I/OPCR 2)
I/O Port Configuration Register 3 (I/OPCR 3)
Counter Timer Preset Register Upper (CTPU 1)
Counter Timer Preset Register Lower (CTPL 1)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
Table 78
86 of 110
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