SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 64
SC28L201A1DGG,118
Manufacturer Part Number
SC28L201A1DGG,118
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,118
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277824118
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
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Philips Semiconductors
9397 750 13138
Product data sheet
8.4.1 Programmable BRG Timer Reload Registers, Upper 0 and Upper 1
8.4.2 Programmable BRG Timer Reload Registers, Lower 0 and Lower 1
8.4 Programmable counters, timers, and baud rate generators
(PBRGPU)
This is the upper byte of the 16-bit value used by the BRG timer in generating a baud rate
clock.
Table 38:
(PBRGPL)
This is the lower byte of the 16-bit value used by the BRG timer in generating a baud rate
clock.
Table 39:
Bit
7:0
Bit
7:0
Symbol
Symbol
PBRGPU - Programmable BRG Timer Reload Registers, Upper 0 and Upper 1
(address 0x27) bit description
PBRGPL - Programmable BRG Timer Reload Registers, Lower 0 and Lower 1
(address 0x26) bit description
Description
8 MSBs of the BRG Timer divisor.
Description
8 LSBs of the BRG Timer divisor.
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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