AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 106
AT89C51CC01
Manufacturer Part Number
AT89C51CC01
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C51CC01.pdf
(167 pages)
2.AT89C51CC01.pdf
(12 pages)
3.AT89C51CC01.pdf
(32 pages)
4.AT89C51CC01.pdf
(29 pages)
Specifications of AT89C51CC01
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
34
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
1.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes
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106
A/T89C51CC01
Table 73. CANPAGE Register
CANPAGE (S:B1h)
CAN Message Object Page Register
Reset Value = 0000 0000b
Table 74. CANCONCH Register
CANCONCH (S:B3h)
CAN Message Object Control and DLC Register
No default value after reset
CONCH 1
Number
Number
CHNB 3
Bit
Bit
7-4
2-0
7-6
3-0
7
7
3
5
4
Bit Mnemonic Description
Bit Mnemonic Description
CONCH 0
CHNB 2
CONCH1:0
CHNB3:0
INDX2:0
DLC3:0
RPLV
AINC
6
6
IDE
CHNB 1
Selection of Message Object Number
The available numbers are: 0 to 14 (see Figure 44).
Auto Increment of the Index (active low)
0 - auto-increment of the index (default value).
1 - non-auto-increment of the index.
Index
Byte location of the data field for the defined message object (see Figure 44).
Configuration of Message Object
CONCH1 CONCH0
Note: The user must re-write the configuration to enable the corresponding bit
in the CANEN1:2 registers.
Reply Valid
Used in the automatic reply mode after receiving a remote frame
0 - reply not ready.
1 - reply ready and valid.
Identifier Extension
0 - CAN standard rev 2.0 A (ident = 11 bits).
1 - CAN standard rev 2.0 B (ident = 29 bits).
Data Length Code
Number of Bytes in the data field of the message.
The range of DLC is from 0 up to 8.
This value is updated when a frame is received (data or remote frame).
If the expected DLC differs from the incoming DLC, a warning appears in the
CANSTCH register.
RPLV
5
5
0
0
1
1
0: disable
1: Launch transmission
0: Enable Reception
1: Enable Reception Buffer
CHNB 0
IDE
4
4
DLC 3
AINC
3
3
INDX2
DLC 2
2
2
INDX1
DLC 1
1
1
4129N–CAN–03/08
INDX0
DLC 0
0
0