AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 97
AT89C51CC01
Manufacturer Part Number
AT89C51CC01
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C51CC01.pdf
(167 pages)
2.AT89C51CC01.pdf
(12 pages)
3.AT89C51CC01.pdf
(32 pages)
4.AT89C51CC01.pdf
(29 pages)
Specifications of AT89C51CC01
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
34
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
1.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes
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4129N–CAN–03/08
Table 59. CANGSTA Register
CANGSTA (S:AAh Read Only)
CAN General Status Register
Reset Value = x0x0 0000b
Number
Bit
7
-
7
6
5
4
3
2
1
0
Bit Mnemonic Description
OVFG
OVFG
ENFG
ERRP
TBSY
RBSY
BOFF
6
-
-
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Overload Frame Flag
This status bit is set by the hardware as long as the produced overload frame
is sent.
This flag does not generate an interrupt
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Transmitter Busy
This status bit is set by the hardware as long as the CAN transmitter
generates a frame (remote, data, overload or error frame) or an ack field. This
bit is also active during an InterFrame Spacing if a frame must be sent.
This flag does not generate an interrupt.
Receiver Busy
This status bit is set by the hardware as long as the CAN receiver acquires or
monitors a frame.
This flag does not generate an interrupt.
Enable On-chip CAN Controller Flag
Because an enable/disable command is not effective immediately, this status
bit gives the true state of a chosen mode.
This flag does not generate an interrupt.
Bus Off Mode
see Figure 49
Error Passive Mode
see Figure 49
5
-
TBSY
4
RBSY
3
ENFG
2
BOFF
1
ERRP
0
97