AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 71

• Manufacturer Part Number: AT89C51CC01
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC01

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 1.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Watchdog Timer
Figure 38. Watchdog Timer
4129N–CAN–03/08
Fwd Clock
RESET
-
T89C51CC01 contains a powerful programmable hardware Watchdog Timer (WDT) that
automatically resets the chip if it software fails to reset the WDT before the selected time
interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc =
12MHz in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis-
ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST
register no instruction in between. When the Watchdog Timer is enabled, it will incre-
ment every machine cycle while the oscillator is running and there is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 96xT
should be serviced in those sections of code that will periodically be executed within the
time required to prevent a WDT reset
Note:
-
WDTPRG
-
When the Watchdog is enable it is impossible to change its period.
WDTRST
-
14-bit COUNTER
Enable
-
2
OSC
1
, where T
0
WR
OSC
=1/F
Control
Decoder
OSC
7-bit COUNTER
. To make the best use of the WDT, it
Outputs
RESET
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