AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 19

• Manufacturer Part Number: AT89LP51RC2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RC2

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 3-2.
Notes:
3722A–MICRO–10/11
DPU
WS
XRS
EXTRAM
DISALE
Symbol
1-0
AUXR = 8EH
Not Bit Addressable
Bit
2-0
1. WS1 is only available in Fast mode. WS1 is forced to 0 in Compatibility mode.
Function
Disable Weak Pull-up. When DPU = 0 all I/O ports in quasi-bidirectional mode have their weak pull-up enabled. When
DPU = 1 all I/O ports in quasi-bidirectional mode have their weak pull-up disabled to reduce power consumption.
Wait State Select. Determines the number of wait states inserted into external memory accesses.
WS1
0
0
1
1
XRAM Size. Selects the size of the on-chip extra RAM (EDATA)
XRS2
0
0
0
0
1
1
1
External RAM Enable. When EXTRAM = 0, MOVX instructions can access the internally mapped portions of the
address space (Extra RAM). Accesses to addresses above internally mapped memory will access external memory. Set
EXTRAM = 1 to bypass the internal memory and map the entire 64KB address space to external memory. The default
state of EXTRAM is set by a user configuration fuse. See
ALE Output. When AO = 0 the ALE pulse is active at 1/3 of the system clock frequency in Compatibility mode and 1/2 of
the system clock frequency in Fast mode. When AO = 1 the ALE is inactive (high) unless an external memory access
occurs. AO must be set to use P4.4 as a general I/O.
AUXR
DPU
7
– Auxiliary Control Register
WS0
0
1
0
1
XRS1
0
0
1
1
0
0
1
Figure 3-9
respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle state of
ALE is controlled by DISALE (AUXR.0). When DISALE = 0 the ALE toggles at a constant rate
when not accessing external memory. When DISALE = 1 the ALE is weakly pulled high. DISALE
must be one in order to use P4.4 as a general-purpose I/O. The WS bits in AUXR can extended
the RD and WR strobes by 1, 2 or 3 cycles as shown in Figures 3-13, 3-14 and 3-15. If a longer
strobe is required, the application can scale the system clock with the clock divider to meet the
requirements (See
WS1
6
(1)
Wait States
0
1
2
3
XRS0
0
1
0
1
0
1
–
and
WS0
Figure 3-10
5
Section 6.8 on page
RD / WR Strobe Width
1 x t
2 x t
2 x t
3 x t
EDATA Size (bytes)
256
512
768 (default)
1024
1152
Reserved
Reserved
CYC
CYC
CYC
CYC
AT89LP51RB2/RC2/IC2 Preliminary
(Fast); 3 x t
(Fast); 15 x t
(Fast)
(Fast)
XRS2
show examples of external data memory write and read cycles,
4
CYC
CYC
Section 24.2 on page
47).
(Compatibility)
(Compatibility)
XRS1
3
XRS0
2
ALE to RD / WR Setup
1 x t
1 x t
2 x t
2 x t
Address Range
0000H–00FFH
0000H–01FFH
0000H–02FFH
0000H–03FFH
0000H–047FH
188.
CYC
CYC
CYC
CYC
Reset Value = 0000 10X0B
(Fast); 1.5 x t
(Fast); 1.5 x t
(Fast)
(Fast)
EXTRAM
1
CYC
CYC
(Compatibility)
(Compatibility)
AO
0
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