AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 109

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.5.3
12.6
12.6.1
7734P–AVR–08/10
Update of Values
Fifty Percent Waveform Configuration
Value Update Synchronization
When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a
Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and
OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not necessary to program
OCRnSAH/L and OCRnRAH/L registers.
The update of PSC waveform registers are done in the following way:
To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary,
all values can be updated at the same time at the end of the cycle by the PSC. The new set of values is cal-
culated by software and the update is initiated by software.
Figure 12-11. Update at the end of complete PSC cycle.
The software can stop the cycle before the end to update the values and restart a new PSC cycle.
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to LOCK
and AUTOLOCK configuration bits, the new whole set of values can be taken into account with the fol-
lowing conditions:
The registers which update is synchronized thanks to LOCK and AUTOLOCK are PSOCn, POM2,
OCRnSAH/L, OCRnRAH/L, OCRnSBH/L and OCRnRBH/L.
See these register’s description starting on
When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.
See “PSC 2 Configuration Register – PCNF2” on page 135.
Software
PSC
• Immediately when the PSC is stopped
• At the PSC end of cycle when the PSC is running
• At the PSC end of cycle following the required condition when LOCK or AUTOLOCK modes are
• When AUTOLOCK configuration is selected, the update of the PSC internal registers will be done at
• When LOCK configuration bit is set, there is no update. The update of the PSC internal registers will
used.
the end of the PSC cycle following a write in the Output Compare Register RB. The AUTOLOCK
configuration bit is taken into account at the end of the first PSC cycle.
be done at the end of the PSC cycle if the LOCK bit is released to zero.
Regulation Loop
Calculation
Cycle
With Set i
Cycle
With Set i
Cycle
With Set i
Writting in
PSC Registers
page
Cycle
With Set i
134.
End of Cycle
Request for
an Update
Cycle
With Set j
AT90PWM81
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