AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 18

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.3
4.3.1
18
EEPROM Data Memory
AT90PWM81
EEPROM Read/Write Access
Figure 4-3.
The AT90PWM81 contains 512 bytes of data EEPROM memory. It is organized as a separate data space,
in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the following, specify-
ing the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
ing” on page
respectively.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, V
slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. For details on how to avoid problems in these situa-
tions
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is exe-
cuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is
executed.
seeSee “Preventing EEPROM Corruption” on page 25.
261, and
On-chip Data SRAM Access Cycles
Address
clk
Data
Data
WR
CPU
RD
“Parallel Programming Parameters, Pin Mapping, and Commands” on page 252
Compute Address
T1
Memory Access Instruction
Table
Address valid
4-2. A self-timing function, however, lets the
T2
Next Instruction
CC
T3
is likely to rise or fall
“Serial Download-
7734P–AVR–08/10