AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 11
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AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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3.5
3.5.1
7734P–AVR–08/10
General Purpose Register File
The X-register, Y-register, and Z-register
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
Figure 3-2
Figure 3-2.
Most of the instructions operating on the Register File have direct access to all registers, and most of them
are single cycle instructions.
As shown in
the first 32 locations of the user Data Space. Although not being physically implemented as SRAM loca-
tions, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-
pointer registers can be set to index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-
bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and
Z are defined as described in
Figure 3-3.
General
Purpose
Working
Registers
X-register
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
shows the structure of the 32 general purpose working registers in the CPU.
Figure
AVR CPU General Purpose Working Registers
The X-, Y-, and Z-registers
3-2, each register is also assigned a data memory address, mapping them directly into
15
7
R27 (0x1B)
15
7
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Figure
3-3.
XH
YH
0
0
Addr.
0x00
0x01
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
7
R26 (0x1A)
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
XL
YL
AT90PWM81
0
0
0
11
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