AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 77
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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7734P–AVR–08/10
• ADC1/ACMP2_OUT, Bit 3
ADC1, Analog to Digital Converter, input channel 1.
ACMP2_OUT, Analog Comparator 2 Output.
• ADC0/ACMP1, Bit 2
ADC0, Analog to Digital Converter, input channel 0
ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the Analog
Comparator.
• PSCOUTR0/PSCINrB – Bit 1
PSCOUTR0: Output 0 of PSCR.
PCSINrB, PSCR Second Alternate Digital Input.
• ACMP3_OUT_A/SS/CLKO – Bit 0
ACMP2_OUT_A, Analog Comparator 2 Alternate Output.
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regard-
less of the setting of DDDn. As a slave, the SPI is activated when this pin is driven low. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDDn. When the pin is forced to be an
input, the pull-up can still be controlled by the PORTDn bit.
CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided system
clock will be output if the CKOUT Fuse is programmed, regardless of the PORTDn and DDDn settings. It
will also be output during reset.
Table 9-7
9-5 on page
Table 9-7.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
and
71.
Table 9-8
Overriding Signals for Alternate Functions PD7..PD4
PD7/
ADC10/ PSCINrA
relates the alternate functions of Port D to the overriding signals shown in
PD6/APM0+
.
PD5/AMP0-
/ADC7
AT90PWM81
PD4/ACMP3M/
ADC2/PSCIN2A
Figure
77
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