AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 33

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.2.5
5.2.6
7734P–AVR–08/10
External Clock
PLL
To drive the device from this external clock source, CLKI should be driven as shown in
the device on an external clock, the CKSEL Fuses or CSEL field must be programmed as shown in
5-1 on page
Figure 5-3.
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as
shown in
Table 5-8.
Notes:
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock fre-
quency while still ensuring stable operation. Refer to
To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency clock input.
This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of PLL must be con-
figured by software..
The internal PLL in AT90PWM81 generates a clock frequency multiplied from nominally 8 MHz input.
The source of the 8 MHz PLL input clock can be selected from three possible sources (See the
on page
•
•
•
The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit PLOCK from
the register PLLCSR is set when PLL is locked.
When selected as clock source by fuse, the PLL multiplication factor is initialized at the value of 6, com-
patible with a 3V supply.
CSUT1..0
SUT1..0
Internal RC Oscillator
Crystal oscillator
External clock
00
01
10
11
34) :
1. Flash Fuse bits.
2. CLKSELR register bits.
Table
(1)
28.
(2)
5-8.
External Clock Drive Configuration
Start-up Times for the External Clock Selection
Start-up Time from
Power-down
6 CK
6 CK
6 CK
External
Signal
Clock
Additional Delay from Reset
14CK + 64 ms
“System Clock Prescaler” on page 38
14CK + 4 ms
14CK
Reserved
(XTAL1)
CLKI
GND
AT90PWM81
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
Figure
for details.
5-3. To run
Figure 5-4
Table
33