AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 229
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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18.4.2
18.4.2.1
18.4.2.2
7734P–AVR–08/10
Digital to Analog Converter input Register – DACH and DACL
DALA = 0
DALA = 1
Table 18-1.
• Bit 2 – DALA: Digital to Analog Left Adjust
Set this bit to left adjust the DAC input data.
Clear it to right adjust the DAC input data.
The DALA bit affects the configuration of the DAC data registers. Changing this bit affects the DAC out-
put on the next DACH writing.
• Bit 1 – Reserved
.
• Bit 0 – DAEN: Digital to Analog Enable bit
Set this bit to enable the DAC,
Clear it to disable the DAC.
DACH and DACL registers contain the value to be converted into analog voltage.
Writing the DACL register forbid the update of the input value until DACH has not been written too. So
the normal way to write a 10-bit value in the DAC register is firstly to write DACL the DACH.
In order to work easily with only 8 bits, there is the possibility to left adjust the input value. Like this it is
sufficient to write DACH to update the DAC value.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
DATS2
1
1
1
1
DATS1
0
0
1
1
DAC Auto Trigger source selection (Continued)
7
-
DAC7
R/W
R/W
0
0
7
DAC9
DAC1
R/W
R/W
0
0
6
-
DAC6
R/W
R/W
0
0
6
DAC8
DAC0
R/W
R/W
0
0
DATS0
0
1
0
1
5
-
DAC5
R/W
R/W
0
0
5
DAC7
-
R/W
R/W
0
0
Description
Reserved
Reserved
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
4
-
DAC4
R/W
R/W
0
0
4
DAC6
-
R/W
R/W
0
0
3
-
DAC3
R/W
R/W
0
0
3
DAC5
-
R/W
R/W
0
0
2
-
DAC2
R/W
R/W
0
0
2
DAC4
-
R/W
R/W
0
0
1
DAC9
DAC1
R/W
R/W
0
0
1
DAC3
-
R/W
R/W
0
0
AT90PWM81
0
DAC8
DAC0
R/W
R/W
0
0
0
DAC2
-
R/W
R/W
0
0
DACH
DACL
DACH
DACL
229
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