ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet - Page 137
ATmega1284RZAP
Manufacturer Part Number
ATmega1284RZAP
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1284RZAP
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
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14.11.9
14.11.10 TIFR1 – Timer/Counter1 Interrupt Flag Register
8059D–AVR–11/09
TIMSK3 – Timer/Counter3 Interrupt Mask Register
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 59) is executed when the ICF3 Flag, located in TIFR3, is set.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF3B Flag, located in
TIFR3, is set.
• Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF3A Flag, located in
TIFR3, is set.
• Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “9.3” on page
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
Bit
(0x71)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
53.) is executed when the TOV3 Flag, located in TIFR3, is set.
ICIE3
R/W
ICF1
R/W
5
0
5
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE3B
OCF1B
R/W
R/W
2
0
2
0
ATmega1284P
OCIE3A
OCF1A
R/W
R/W
1
0
1
0
TOIE3
TOV1
R/W
R/W
0
0
0
0
TIMSK3
TIFR1
137
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