ATmega644R212 Atmel Corporation, ATmega644R212 Datasheet - Page 125

• Manufacturer Part Number: ATmega644R212
• Manufacturer: Atmel Corporation

Specifications of ATmega644R212

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

9.8
9.8.1
9.8.2
8111C–MCU Wireless–09/09
Bit
+0x18
Read/Write
Reset Value
Automatic Filter Tuning (FTN)
Overview
Register Description
FTN_START
R/W
7
0
The FTN is incorporated to compensate device tolerances for temperature, supply voltage varia-
tions as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to
correct the analog baseband filter transfer function and the PLL loop-filter time constant, refer to
Section 4. “General Circuit Description” on page
An FTN calibration cycle is initiated automatically when entering the TRX_OFF state from the
SLEEP, RESET or P_ON states.
Although receiver and transmitter are very robust against these variations, it is recommended to
initiate the FTN manually if the radio transceiver does not use the SLEEP state. If necessary, a
calibration cycle is to be initiated in states TRX_OFF, PLL_ON or any receive state. This applies
in particular for the High Data Rate Modes with a much higher sensitivity against BPF transfer
function variations. The recommended calibration interval is 5 min or less.
Register 0x18 (FTN_CTRL):
This register controls the operation of the filter tuning network calibration loop.
• Bit 7 - FTN_START
FTN_START = 1 initiates the filter tuning network calibration. When the calibration cycle has fin-
ished after at most 25 µs the register bit is automatically reset to 0.
• Bit [6:0] - Reserved
R/W
6
1
R/W
5
0
R/W
4
1
Reserved
R/W
3
1
10.
R/W
2
0
R/W
1
0
AT86RF231
R/W
0
0
FTN_CTRL
125