ATmega644R212 Atmel Corporation, ATmega644R212 Datasheet - Page 86

• Manufacturer Part Number: ATmega644R212
• Manufacturer: Atmel Corporation

Specifications of ATmega644R212

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

8.2.3
8.2.4
8111C–MCU Wireless–09/09
Automatic FCS generation
Automatic FCS check
The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1 (reset
value). This allows the AT86RF231 to compute the FCS autonomously. For a frame with a frame
length specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame
Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame
Buffer.
If the radio transceivers automatic FCS generation is enabled, the Frame Buffer write access
can be stopped right after MAC payload. There is no need to write FCS dummy bytes.
In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK
frame is always automatically generated by the AT86RF231, independent of the
TX_AUTO_CRC_ON setting.
Example:
A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a Frame Buffer
write access of five bytes (the last two bytes can be omitted). The first three bytes are used for
FCS generation; the last two bytes are replaced by the internally calculated FCS.
An automatic FCS check is applied on each received frame with a frame length N
bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set if the FCS of a received frame is valid.
The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the
next TRX_END interrupt caused by a new frame reception.
In RX_AACK mode, if FCS of the received frame is not valid, the radio transceiver rejects the
frame and the TRX_END interrupt is not issued.
In TX_ARET mode, the FCS and the sequence number of an ACK is automatically checked. If
one of these is not correct, the ACK is not accepted.
AT86RF231
2. Register
86