ATmega644R212 Atmel Corporation, ATmega644R212 Datasheet - Page 57
ATmega644R212
Manufacturer Part Number
ATmega644R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega644R212
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
4
Eeprom (bytes)
2048
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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8111C–MCU Wireless–09/09
Only second level filter rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, are applied to
the received frame.
Table 7-8 on page 57
Table 7-8.
If the radio transceiver is in promiscuous mode, second level of filtering according to
IEEE 802.15.4-2006, section 7.5.6.2, is applied to a received frame. However, an IRQ_3
(TRX_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit
RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the
reception of a frame with a valid FCS.
If a device, operating in promiscuous mode, receives a frame with a valid FCS which further
passed the third level of filtering according to IEEE 802.15.4-2006, section 7.5.6.2, an acknowl-
edgement frame would be transmitted. According to the definition of the promiscuous mode a
received frame shall not be acknowledged, even if it is requested. Thus register bit
AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set to 1.
In all receive modes an IRQ_5 (AMI) interrupt is issued, when the received frame matches the
node's address according to the filter rules described in
page 61
Alternatively, in Basic Operating Mode RX_ON state, when a valid PHR is detected, an IRQ_2
(RX_START) is generated and the frame is received. The end of the frame reception is signal-
ized with an IRQ_3 (TRX_END). At the same time the register bit RX_CRC_VALID (register
0x06, PHY_RSSI) is updated with the result of the FCS check (see
Sequence (FCS)” on page
RX_CRC_VALID bit needs to be checked in order to dismiss corrupted frames.
0x20,0x21
0x22,0x23
Register
Address
0x24,
0x2B
0x2E
0x2E
0x17
...
Register
Configuration of Promiscuous Mode
Bits
7:6
4
1
shows the typical configuration of a device operating promiscuous mode.
Register Name
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
...
IEEE_ADDR_7
AACK_PROM_MODE
AACK_DIS_ACK
AACK_FVN_MODE
85). According to the promiscuous mode definition the
Description
Address shall be set: 0x00
1: Enable promiscuous Mode
1: Disable generation of acknowledgment
Controls the ACK behavior, depending on FCF
frame version number
0x00: acknowledges only frames with version
number 0, i.e. according to IEEE 802.15.4-2003
frames
0x01: acknowledges only frames with version
number 0 or 1, i.e. frames according to
IEEE 802.15.4-2006
0x10: acknowledges only frames with version
number 0 or 1 or 2
0x11: acknowledges all frames, independent of
the FCF frame version number
Section 7.2.3.5 “Frame Filtering” on
Section 8.2 “Frame Check
AT86RF231
57
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