ATmega644R212 Atmel Corporation, ATmega644R212 Datasheet - Page 24

• Manufacturer Part Number: ATmega644R212
• Manufacturer: Atmel Corporation

Specifications of ATmega644R212

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

6.3
6.3.1
8111C–MCU Wireless–09/09
Bit
+0x04
Read/Write
Initial Value
Radio Transceiver Status information
Register Description - SPI Control
PA_EXT_EN
R/W
7
0
IRQ_2_EXT_EN
Each SPI access can be configured to return status information of the radio transceiver
(PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO.
The content of the radio transceiver status information can be configured using register bits
SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send
on MISO to the microcontroller is set to 0x00.
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating modes and
settings of the radio transceiver.
• Bit 7 - PA_EXT_EN
Refer to
• Bit 6 - IRQ_2_EXT_EN
Refer to
• Bit 5 - TX_AUTO_CRC_ON
Refer to
• Bit 4 - RX_BL_CTRL
Refer to
• Bit [3:2] - SPI_CMD_MODE
Each SPI transfer returns bytes back to the SPI master. The content of the first byte can be con-
figured using register bits SPI_CMD_MODE. The transfer of the following status information can
be configured as follows:
Table 6-3.
• Bit 1 - IRQ_MASK_MODE
Refer to
• Bit 0 - IRQ_POLARITY
Refer to
R/W
Register Bit
SPI_CMD_MODE
6
0
Section 11.5 “RX/TX Indicator” on page
Section 11.6 “RX Frame Time Stamping” on page
Section 8.2 “Frame Check Sequence (FCS)” on page
Section 11.7 “Frame Buffer Empty Indicator” on page
Section 6.6 “Interrupt Logic” on page
Section 6.6 “Interrupt Logic” on page
TX_AUTO_CRC_ON
Radio Transceiver Status Information - PHY_STATUS
R/W
5
1
RX_BL_CTRL
R/W
4
Value
0
0
1
2
3
R/W
Description
default (empty, all bits 0x00)
monitor TRX_STATUS register; see
monitor PHY_RSSI register; see
monitor IRQ_STATUS register; see
3
0
SPI_CMD_MODE
29.
29.
147.
R/W
2
0
150.
IRQ_MASK_MODE
152.
85.
R/W
1
0
Section 8.3
Section 6.6
Section 7.1.5
AT86RF231
IRQ_POLARITY
R/W
0
0
TRX_CTRL_1
24