ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 17

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

In-System
Programmable
Flash Program
Memory
SRAM Data
Memory
1477K–AVR–08/10
Figure 18. On-chip Data SRAM Access Cycles
The ATtiny26(L) contains 2K bytes On-chip In-System Programmable Flash memory for pro-
gram storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 1K x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny26(L) Pro-
gram Counter – PC – is 10 bits wide, thus addressing the 1024 program memory addresses, see
“Memory Programming” on page 107 for a detailed description on Flash data downloading. See
“Program and Data Addressing Modes” on page 11 for the different program memory address-
ing modes.
Figure 19. SRAM Organization
Figure 19 above shows how the ATtiny26(L) SRAM Memory is organized.
The lower 224 Data Memory locations address the Register File, the I/O Memory and the inter-
nal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next
128 locations address the internal data SRAM.
System Clock Ø
I/O Registers
Register File
R29
R30
R31
$3D
$3E
$00
$01
$02
$3F
R0
R1
R2
Address
…
...
Data
Data
WR
RD
Prev. Address
T1
Address
T2
T3
Data Address Space
Internal SRAM
$00DE
$001D
$001E
$005D
$005E
$00DF
$0000
$0001
$0002
$001F
$0020
$0021
$0022
$005F
$0060
$0061
…
...
...
T4
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