ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 38

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Idle Mode
ADC Noise
Reduction Mode
Power-down Mode
38
ATtiny26(L)
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask is set (one). The activity on the external INT0 pin that activates the
interrupt is defined in the following table.
Table 18. Interrupt 0 Sense Control
Note:
When the SM1..0 bits are written to “00”, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing Analog Comparator, ADC, USI, Timer/Counters, Watch-
dog, and the interrupt system to continue operating. This sleep mode basically halts clk
clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USI Start and Overflow interrupts. If wake-up from the Analog
Comparator interrupt is not required, the Analog Comparator can be powered down by setting
the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce
power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when
this mode is entered.
When the SM1..0 bits are written to “01”, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the USI
start condition detection, and the Watchdog to continue operating (if enabled). This sleep mode
basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, USI start condition interrupt, an EEPROM ready interrupt, an External Level Interrupt on
INT0, or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
When the SM1..0 bits are written to “10”, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the
USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-
nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an External
Level Interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basi-
cally halts all generated clocks, allowing operation of asynchronous modules only.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
reset time-out period, as described in “Clock Sources” on page 25.
Note that if a level triggered external interrupt or pin change interrupt is used from Power-down
mode, the changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise.
ISC01
FLASH
0
0
1
1
, while allowing the other clocks to run.
1. When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable
bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are changed.
ISC00
0
1
0
1
I/O
, clk
Description
The low level of INT0 generates an interrupt request.
Any change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
CPU
, and clk
FLASH
(1)
, while allowing the other clocks to run.
1477K–AVR–08/10
CPU
and