ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 24

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Internal PLL for Fast
Peripheral Clock
Generation – clk
24
ATtiny26(L)
PCK
The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from nomi-
nally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC
Oscillator which is automatically divided down to 1 MHz, if needed. See the Figure 21 on page
24. When the PLL reference frequency is the nominal 1 MHz, the fast peripheral clock is 64
MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock
source for Timer/Counter1.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register
will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC
Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency satu-
rates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be
noted that the PLL in this case is not locked any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1
MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only
when the PLLE bit in the register PLLCSR is set or the PLLCK Fuse is programmed (“0”). The bit
PLOCK from the register PLLCSR is set when PLL is locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep
modes.
Figure 21. PCK Clocking System
XTAL1
XTAL2
RC OSCILLATOR
OSCCAL
OSCILLATORS
PLLE
1
2
4
8 MHz
PLLCK &
TO 1 MHz
CKSEL
FUSES
DIVIDE
PLL
64x
Detector
Lock
DIVIDE
BY 4
1477K–AVR–08/10
PLOCK
CK
PCK