ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 81

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Register
Descriptions
USI Data Register –
USIDR
USI Status Register –
USISR
1477K–AVR–08/10
The USI uses no buffering of the serial register, i.e., when accessing the Data Register (USIDR)
the serial register is accessed directly. If a serial clock occurs at the same cycle the register is
written, the register will contain the value written and no shift is performed. A (left) shift operation
is performed depending of the USICS1..0 bits setting. The shift operation can be controlled by
an external clock edge, by a Timer/Counter0 overflow, or directly by software using the USICLK
strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external
data input (DI/SDA) and the external clock input (SCK/SCL) can still be used by the Shift
Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch
to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) dur-
ing the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1),
and constantly open when an internal clock source is used (USICS1 = 0). The output will be
changed immediately when a new MSB written as long as the latch is open. The latch ensures
that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register (DDRB2/1) to the pin must be set to one for
enabling data output from the Shift Register.
The Status Register contains interrupt flags, line status flags and the counter value.
Note that doing a Read-Modify-Write operation on USISR Register, i.e., using the SBI or CBI
instructions, will clear pending interrupt flags. It is recommended that register contents is altered
by using the OUT instruction only.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition is
detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &
USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF
bit. Clearing this bit will release the start detection hold of SCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all four sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.
Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
Bit
$0F ($2F)
Read/Write
Initial Value
Bit
$0E ($2E)
Read/Write
Initial Value
USISIF
R/W
MSB
R/W
7
0
7
0
USIOIF
R/W
6
0
R/W
6
0
USIPF
R/W
5
0
R/W
5
0
USIDC
R
4
0
R/W
4
0
USICNT3
R/W
3
0
R/W
3
0
USICNT2
R/W
2
0
R/W
2
0
USICNT1
R/W
R/W
1
0
1
0
USICNT0
LSB
R/W
R/W
0
0
0
0
USIDR
USISR
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