ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 108

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.7.2
8331A–AVR–07/11
PRPA/B – Power Reduction Port A/B Register
• Bit 7 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 6 – USB: USB Module
Setting this bit stops the clock to the USB module. When this bit is cleared, the peripheral should
be reinitialized to ensure proper operation.
• Bit 5 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 4 – AES: AES Module
Setting this bit stops the clock to the AES module. When this bit is cleared, the peripheral should
be reinitialized to ensure proper operation.
• Bit 3 – EBI: External Bus Interface
Setting this bit stops the clock to the external bus interface. When this bit is cleared, the periph-
eral should be reinitialized to ensure proper operation.
• Bit 2 – RTC: Real-Time Counter
Setting this bit stops the clock to the real-time counter. When this bit is cleared, the peripheral
should be reinitialized to ensure proper operation.
• Bit 1 – EVSYS: Event System
Setting this stops the clock to the event system. When this bit is cleared, the module will con-
tinue as before it was stopped.
• Bit 0 – DMA: DMA Controller
Setting this bit stops the clock to the DMA controller. This bit can be set only if the DMA control-
ler is disabled.
Note:
• Bit 7:3 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 – DAC: Power Reduction DAC
Setting this bit stops the clock to the DAC. The DAC should be disabled before stopped.
Bit
+0x01/+0x02
Read/Write
Initial Value
Disabling of analog modules stops the clock to the analog blocks themselves and not only the
interfaces.
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
Atmel AVR XMEGA AU
3
–
R
0
DAC
R/W
2
0
ADC
R/W
1
0
R/W
AC
0
0
PRPA/B
108