ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 262

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.3.3
21.3.4
21.3.5
21.3.6
8331A–AVR–07/11
Bit Transfer
Address Packet
Data Packet
Transaction
As illustrated by
period of the SCL line. Consequently the SDA value can only be changed during the low period
of the clock. This is ensured in hardware by the TWI module.
Figure 21-4. Data validity.
Combining bit transfers results in the formation of address and data packets. These packets
consist of eight data bits (one byte) with the most-significant bit transferred first, plus a single-bit
not-acknowledge (NACK) or acknowledge (ACK) response. The addressed device signals ACK
by pulling the SCL line low during the ninth clock cycle, and signals NACK by leaving the line
SCL high.
After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is
always transmitted by the master. A slave recognizing its address will ACK the address by pull-
ing the data line low for the next SCL cycle, while all other slaves should keep the TWI lines
released and wait for the next START and address. The address, R/W bit, and acknowledge bit
combined is the address packet. Only one address packet for each START condition is allowed,
also when 10-bit addressing is used.
The R/W bit specifies the direction of the transaction. If the R/W bit is low, it indicates a master
write transaction, and the master will transmit its data after the slave has acknowledged its
address. If the R/W bit is high, it indicates a master read transaction, and the slave will transmit
its data after acknowledging its address.
An address packet is followed by one or more data packets. All data packets are nine bits long,
consisting of one data byte and an acknowledge bit. The direction bit in the previous address
packet determines the direction in which the data are transferred.
A transaction is the complete transfer from a START to a STOP condition, including any
repeated START conditions in between. The TWI standard defines three fundamental transac-
tion modes: Master write, master read, and a combined transaction.
Figure 21-5 on page 263
action by issuing a START condition (S) followed by an address packet with the direction bit set
to zero (ADDRESS+W).
SDA
SCL
Figure
21-4, a bit transferred on the SDA line must be stable for the entire high
illustrates the master write transaction. The master initiates the trans-
DATA
Valid
Change
Allowed
Atmel AVR XMEGA AU
262